The present invention relates to a synchronizing system and a circuit therefor, and to a technique suitable for use in, for example, a modulator and demodulator (hereinafter called "MODEM").
The term "MODEM" is known as an acronym for modulator/demodulator that transmits data therefrom over an analog transmission line such as a telephone line. There are various kinds of communication systems or mod/demod systems. However, LSIs (Large-Scale Integration) have been promoted as semiconductor devices for realizing the MODEM.
Regarding the current circumstances of Large-Scale Integration of the MODEM, small-scale integration, i.e., LSI is indispensable to the fact that the MODEM is rendered high-performance and multi-functioned as described in Japanese Technical Journal "Electronics", p.p. 51-55, October 1984. In particular, each of high-speed MODEMs having transmission speeds of 4800 bps, 9600 bps or the like have recently been used with a digital signal processor (hereinafter called merely "DSP") to utilize a digital signal processing technique which has been created with the development of the utilization technology. Incorporated inside the DSP are a RAM (Random Access Memory) for temporarily storing data therein, a data ROM (Read-Only Memory) for storing therein constants required to perform arithmetic calculation, a high-speed parallel multiplier, an addition/subtraction and arithmetic and logic unit (ALU), an input/output port (I/O port) and an instruction ROM for writing signal processing procedures therein. In particular, the DSP is normally provided at its inside with data bus lines and two sets of RAMs to efficiently execute the calculation. Otherwise, some designs such as an address pointer for exhibiting high level functions and performing high-speed calculation, interrupt control, automatically-repeated instruction functions have been made in the DSP.
On the other hand, even when the modulation/demodulation is subjected to the digital signal processing by means of the above-described DSP, an analog circuit is required to provide an interface to be linked to lines. Even at this portion, an analog front end LSI is used. The analog front end LSI is composed principally of a transmit-receive filter for eliminating stop-band signals, an A/D (Analog/Digital) converter, and a D/A (Digital/Analog) converter. In addition to the above LSI, there is provided another LSI in which an attenuator (ATT) for setting the level of a signal or the like is incorporated.
A low-speed MODEM having the transmission speed of 1200 bps or less has been used with a FSK (frequency shift keying) or PSK (phase shift keying) modulation system. Since both systems can be realized by using circuits having simple circuit structures and are less affected by the line distortion, thereby making it unnecessary to have an automatic equalizer, one-chip type MODEM has been realized in which digital and analog units have been integrated into a single semiconductor chip. An example of such one-chip type MODEM has been described in the article "IEEE Journal of Solid State Circuits" published in U.S.A., Vol. SC-19, No. 6, pp. 869-877. The MODEM described in this article is of a low-speed MODEM in which the FSK modulation system is only incorporated, but which shows one orientation for the LSI. Namely, the MODEM has nine data modes and nineteen operation modes. The mod/demod required to perform the operations of the MODEM in these modes and all functions of filters or the like have been realized by the digital signal processing of two DSPs which are integrated together with the A/D converter and the D/A converter into one chip. Otherwise, this MODEM has a serial interface, a loop back test function and the like incorporated therein, which have been determined by the RC232C interface standard and the V.24 interface standard.
Regarding hardware, each of the two DSPs has a data RAM, a coefficient ROM, an instruction ROM. The two DSPs are activated in a separate manner, respectively. In addition, each of the A/D converter and the D/A converter serves to select the high sampling rate based on the sampling theorem developed by Nyquist. However, they can also select the higher sampling rate to eliminate turnaround noise caused by the sampling. As the A/D converter is used with a complement-type delta sigma system, wherein a sequential analog circuit is omitted and digital circuits such as decimeters, interpolators are used in combination, thereby obtaining an A/D converted signal at the desired sampling rate. Therefore, this system can bring about features that, even when the digital circuits are principally integrated into one chip, they have less variations in characteristics as semiconductor devices and good stability. As a result, the reproducibility of the characteristics is offered even if they are mass-produced, and a number of operation modes and complex functions can be realized by software control without increasing the size of the chip to that extent.
In such a conventional MODEM as being typical of the MODEM described in the above-described article, a DPLL (Digital Phase-Locked Loop) operation is used to synchronize the MODEM with a terminal device such as a microcomputer, and values counted by a programmable timer (digital VCO) are changed corresponding to the difference in clock phase between the two. This DPLL is disclosed in the technical Journal "The Collection of Design Examples of PLL Control Circuits" published by Kabushiki Kaisha Triceps., p.p. 34, issued on Dec. 18, 1987. Notwithstanding the above MODEM, a synchronous pull-in or lead-in method for a PLL circuit has been disclosed in Japanese Patent Laid-Open No. 63-286082.
The DPLL employed in the conventional MODEM or the like is designed to make a fine adjustment of the programmable timer (programmable counter) in accordance with the result of phase comparison for each baud timing, i.e., incrementing the value of a pulse by +1 or decrementing the same by -1 as in the DPLL described in the above-described article, thereby effecting the synchronization of the DPLL. Therefore, it has definitely been shown by the investigation of the present inventors that several tens of bauds or so are required to make a phase conformity, thereby causing a long lead-in time.
Here, the term "Baud" generally shows a unit of signaling speed. The signaling speed is represented by the number of unit elements per second, which constitute Morse codes.
Since the MODEM or the like has been used with a fixed oscillator circuit having the same oscillating frequency as the terminal device, the synchronization of the DPLL can be performed instantly by resetting the programmable timer of the DPLL in synchronism with the clock from the terminal device as in the synchronous lead-in method for the PLL circuit, which has been described in Japanese Patent Laid-Open No. 63-286082. However, since 1 baud is made up of a plurality of bits and a taken-in-data is made for each baud in the MODEM or the like, the baud timing signal, i.e., baud timing is formed therein continuously. Therefore, when the programmable timer is reset by an external clock which is in asynchronism with the baud timing signal, the continuity of the baud timing is broken. Thus, the above-described synchronous lead-in method for the PLL circuit cannot be utilized as it is.
The MODEM is connected to the terminal device by connectors. Therefore, there is a case where a desired clock is not supplied from the terminal device due to the imperfect contact of the connectors therebetween and their disconnection. It is thus necessary to provide functions for determining or detecting whether or not the external clock is inputted. In the conventional MODEM, the number of outputs of +1 or -1 produced plural times continuously is counted by making use of the phase comparison output of the DPLL, to thereby detect the presence or absence of the supply of the external clock. Namely, when the external clock is not supplied, the inputted clock is fixed to a low or high level Therefore, +1 or -1 continues to be outputted as the phase comparison output. This clock detection method is required to investigate whether or not the above -1 or +1 continues to be outputted over a longer period of time than the relatively long lead-in time for the DPLL. Therefore, a longer period of time should be spent to judge whether or not the clock is detected. As a result, it has definitely been shown by the investigation of the present inventors that the conventional MODEM is accompanied by the problem that a relatively long period of time is required to receive a request-to-transmit-data from the terminal device for thereby performing the input of data to be transmitted.